1. Field of the Invention
The present invention relates to the semiconductor device using first and second power MOSFETs (MOS transistors), and more particularly to the semiconductor device which is incorporated with a transformer, a photo-coupler and the like and includes an analog switch, and uses as a solid state relay.
2. Description of the Related Art
Conventionally, two power MOS transistors are connected in series to a solid state relay, a slic for telephone and like. Regarding this connection, as shown in FIG. 1, sources S1 and S2 of power MOS transistors Q1 and Q2 are connected in common with each other.
As shown in FIG. 1, a control signal is sent between a common gate G and an electrode of a common source S, so that both transistors Q1 and Q2 are in an ON state or OFF state If the control signal (Sig) is send therebetween and the common gate G is positive and the common source S is negative, both transistors Q1 and Q2 are in an ON state, and a current in positive and negative directions can be supplied between drains D1 and D2 due to the property of the power MOS transistor. In the OFF state, either positive or negative voltage is applied between the drain D1 of the transistor Q1 and the drain D2 of the transistor Q2. However, due to breakdown voltage (reverse bias) between the drain and the source of either the transistors Q1 or Q2, the current is prevented from flowing through the drains D1 and D2.
FIGS. 2 and 3 show a circuit wherein a transformer T and a photo-coupler PC are incorporated into the circuit of FIG. 1. In these drawings, reference numeral 11 denotes a light-emitting element, reference numeral 12 denotes a photoelectric transfer element, and reference numeral 13 denotes a resistor.
In FIG. 2, transistors Q1 and Q2 have a single MOS power transistor chip, respectively. In FIG. 3, there are used four semiconductor chips for transistors Q1, Q2, photoelectric transformer element 12, and light-emitting element 11.
Moreover, in a transformer-type structure of FIG. 2, an input signal IN is used in only a case when an ac input is supplied by the transformer. In a case of FIG. 3, an input signal IN can be used in a case when a dc input is supplied.
Generally, the power MOS transistor has the structure as shown in FIG. 4. In the drawing, reference numeral 21 denotes an insulating film, 22: an N.sup.+ layer, 23: a P layer, 24: an N.sup.- layer, 25: an N.sup.+ layer, 26: a substrate of a drain electrode, and D: a whole drain. In the structure shown in FIGS. 1 to 4, there are used two semiconductor chips as common sources (S1, S2) in a transistor section of FIG. 5.
Due to this, since the connection between the chips of the power MOS transistors Q1 and Q2 is made by a wire bonding, there are problems in reliance on such a connection, increase in the number of assembly. Moreover, since the structure of the frame for die bonding becomes complicated, cost of manufacture is increased.